EE 382N Literature Survey

1. Introduction The objective of modern superscalar processors is to maximize the instruction-level parallelism (ILP) that can be extracted from programs. The most basic method used for extracting more ILP from programs is out-of-order execution [1]. Unfortunately, out-of-order execution by itself does not provide a desired level of ILP. The program's control flow [2] and data flow [3] impose serious limits on the level of parallelism that can be extracted. Therefore, most modern processors employ aggressive branch prediction mechanisms to relax the control flow constraints that limit the ILP. To overcome the data-flow limits, researchers have suggested the use of data speculation [3,4,5], but these schemes have not yet been implemented in superscalar processors. In this paper, we would like to survey a number of published methods for increasing the ILP by relaxing the constraints imposed by memory dependences. In particular, we will survey methods for dynamic memory disambiguation and memory renaming. In Section 2, we will discuss the importance of relaxing the memory data-flow constraints and discuss the distinctions and similarities between memory disambiguation and memory renaming. Section 3 will present a survey of recent research articles published on both topics and will discuss the advantages and shortcomings of each approach. Section 4 will discuss the differences between those mechanisms and comment on their effectiveness. In Section 5, we will describe how some modern processors tackle the memory dependence problem.